1. Field of the Invention
The present invention relates to etching methods used in the fabrication of integrated electronic circuits in a semiconductor substrate such as silicon, particularly a combined contact etch and planarization in a single mask process.
An electronic circuit is chemically and physically integrated into a substrate such as a silicon wafer by patterning regions in the substrate, and by patterning layers on the substrate. These regions and layers can be conductive, for conductor and resistor fabrication, or insulative, for insulator and capacitor fabrication. They can also by of differing conductivity types, which is essential for transistor and diode fabrication. Degrees of resistance, capacitance, or conductivity are controllable, as are the physical dimensions and locations of the patterned regions and layers, making circuit integration possible. Fabrication can be quite complex and time consuming, and therefore expensive. It is thus a continuing quest of those in the semiconductor fabrication business to reduce fabrication times and costs of such devices in order to increase profits. Any simplified processing step or combination of processes at a single step becomes a competitive advantage.
2. Description of the Related Art
A situation where a process simplification is desirable is in dielectric ("oxide") planarization and contact etch steps, particularly for contacts 1.2 microns or less across. Planarization is necessary because the distance between the valleys and peaks in the oxide is so large that a subsequent layer such as photoresist ("resist") or metal is difficult to pattern due to differences in focusing and exposure requirements between the peaks and valleys, due to different elevations, and due to the tendency for the subsequenct layer to thin out at the peaks and pool in the valleys. "Contact etch" refers to the etching of holes, or contacts, through an intermediate layer such as oxide, so that a conductive layer such as metal on top of the insulative oxide can contact a layer underneath the oxide.
"Reflow", where a layer of oxide is heated sufficiently to cause it to smooth out, provides a degree of planarization. This technique along is not always satisfactory because the high temperature required for adequate reflow may also affect the semiconductor structures under fabrication.
Plasma or "dry" etching is an ideal technology for performing both planarization and contact etch. Plasma offers easy control of the resist-to-oxide etch rate ratio, ideally 1:1 for planarization. Plasma also offers anisotropic etchability, appropriate for making contact walls vertical, which is desirable. A camber or slope in the upper contact wall may also be desirable, to allow easy flow of a subequent layer into the contact during deposition. This slope can be done using plasma techniques or by well known chemical or "wet" etch methods.
Conventionally, an oxide layer is first planarized and then contacts are etched in the oxide before a subsequent metal deposition. In planarization, resist is layered on oxide, as illustrated in FIG. 1, and then etched back at a 1:1 etch rate ratio (resist to oxide), as shown in FIG. 2. Contact etch is done by patterning a mask of resist on the oxide, isotropically etching to slope the contacts, and then finishing with a more anisotropic etch to produce near-vertical slope near the bottom of the contact. The resist is then stripped and the wafer stands ready as shown in FIG. 3 for metal deposition. Although both of these etches can be done dry, the isotropic etch step is often done wet.
It is desirable to perform planarization and contact etch using one resist mask layer instead of two. It is further desirable to perform this entirely by dry etching.